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? 2012 microchip technology inc. preliminary ds22300a-page 1 mcp7952x/mcp7951x device selection table timekeeping features: ? real-time clock/calendar: - hours, minutes, seconds, hundredth of seconds, day of week, month, year, leap year ? crystal oscillator requires external 32,768 khz tuning fork crystal and load capacitors. ? clock out function: - 1hz, 4.096 khz, 8.192 khz, 32.768 khz ? 2 programmable alarms ? programmable open drain output ? alarm or interrupt ? on-chip digital trimming/calibration: - +/- 255 ppm range in 1 ppm steps ? power-fail time-stamp @ battery switchover: - logs time when v cc fails and v cc is restored low-power features: ? wide operating voltage: -v cc : 1.8v to 3.6v -v bat : 1.3v to 3.6v ? low operating current: -v cc standby current < 1ua @ 3v -v bat timekeeping current: <700na @ 1.8v ? automatic battery switchover from v cc to v bat : - backup power for timekeeping and sram retention user memory: ? 64-byte battery-backed sram ? 2 kbit and 1 kbit eeprom memory: - software block write-protect (?, ?, or entire array) - write page mode (up to 8 bytes) - endurance: 1m erase/write cycles ? 128-bit unique id in protected area of eeprom: - available blank or preprogrammed - eui-48? or eui-64? mac address - unlock sequence for user programming operating ranges: ? spi clock speed up to 5 mhz ? operating temperature ranges: - industrial (i temp): -40c to +85c. ? packages include 10-lead msop and tdfn package types (not to scale) part number sram (bytes) eeprom (kbits) unique id mcp79520 64 2 blank mcp79510 64 1 blank MCP79521 64 2 eui-48 ? mcp79511 64 1 eui-48 ? mcp79522 64 2 eui-64 ? mcp79512 64 1 eui-64 ? x1 x2 v bat vcc mfp 1 2 3 4 mcp795xx msop/tdfn cs v ss sck so si 5 6 7 10 9 8 note: mcp795xx is used in this document as a generic part number for the mcp7951x, mcp7952x devices. 3v spi real-time clock calendar with battery switchover
mcp7952x/mcp7951x ds22300a-page 2 preliminary ? 2012 microchip technology inc. description: the mcp795xx is a low-power real-time clock/ calendar (rtcc) that uses digital trimming compen- sation for an accurate clock/calendar, an interrupt out- put to support alarms and events, a power sense circuit that automatically switches to the backup sup- ply, nonvolatile memory for safe data storage and sev- eral enhanced features that support system requirements. along with a low-cost 32,768 khz crystal, this rtcc tracks time using several internal registers and then communicates the data over a 5 mhz spi bus that is fast enough to support a programmable millisecond alarm. the device is fully accessible through the serial inter- face, while v cc is between 1.8v and 3.6v, but can operate down to 1.3v through the backup supply con- nected to the v bat input for timekeeping and sram retention only. as part of the power sense circuit, a time saver function is implemented to store the time when main power is lost and again, when power is restored to log the duration of a power failure. along with the on-board serial eeprom and battery- backed sram, a 128-bit protected space is available for a unique id. this space can be ordered preprogrammed with a mac address, or blank for the user to program. this clock/calendar automatically adjusts for months with fewer than 31 days including corrections for leap years. the clock operates in either 24-hour or 12-hour format with am/pm indicator and settable alarm(s). using the external crystal, the mfp pin can be set to generate a number of output frequencies. figure 1-1: block diagram x1 x2 v bat cs v ss v cc mfp sck so si osc clkout divider spi eeprom sram time-stamp id alarms v bat switchover
? 2012 microchip technology inc. preliminary ds22300a-page 3 mcp7952x/mcp7951x 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ................................................................................................................. -0.6v to +6.5v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature under bias................................................................................................. .............. -40c to +85c esd protection on all pins..................................................................................................... ..................................... 4 kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics industrial (i): t amb = -40c to +85c v cc = 1.8v to 3.6v param. no. sym. characteristic min. max. units test conditions d001 v ih 1 high-level input voltage .7 v cc v cc +1 v d002 v il 1 low-level input voltage -0.3 0.3v cc vv cc ??? 2.5v d003 v il 2 -0.3 0.2v cc vv cc < 2.5v d004 v ol low-level output voltage ?0.4vi ol = 2.1 ma d005 v ol ?0.2vi ol = 1.0 ma, v cc < 2.5v d006 v oh high-level output voltage v cc -0.5 ? v i oh = -400 ? a d007 i li input leakage current 1 ? acs = v cc , v in = v ss to v cc d008 i lo output leakage current 1 ? acs = v cc , v out = v ss to v cc d009 c int internal capacitance (all inputs and outputs) ?7pft amb = 25c, clk = 1.0 mhz v cc = 5.0v ( note 1 ) d010 i cc read operating current ? 3 ma v cc = 3.6v; f clk = 5 mhz so = open d011 i dd write write current ? 5 ma v cc = 3.6v d012 i bat v bat current ? 700 na v bat = 1.8v @ 25c ( note 2 ) d013 v trip v bat change over 1.3 1.7 v 1.5v typical at t amb = 25c d014 vccft v cc fall time 300 ? sfrom v trip (max) to v trip (min) d015 vccrt v cc rise time 0 ? sfrom v trip (min) to v trip (max) d016 v bat v bat voltage range 1.3 3.6 v ? d017 i ccs standby current ? 1 ? a? note 1: this parameter is periodically sampled and not 100% tested. 2: with oscillator running.
mcp7952x/mcp7951x ds22300a-page 4 preliminary ? 2012 microchip technology inc. table 1-2: ac characteristics ac characteristics industrial (i): t amb = -40c to +85c v cc = 1.8v to 3.6v param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency ? ? 5 3 mhz mhz 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 2t css cs setup time 100 150 ? ? ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 3t csh cs hold time 100 150 ? ? ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 4t csd cs disable time 50 ? ns ? 5 tsu data setup time 20 30 ? ? ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 6t hd data hold time 40 50 ? ? ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 7t r clk rise time ? 100 ns ( note 1 ) 8t f clk fall time ? 100 ns ( note 1 ) 9t hi clock high time 100 150 ? ? ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 10 t lo clock low time 100 150 ? ? ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 11 t cld clock delay time 50 ? ns ? 12 t cle clock enable time 50 ? ns ? 13 t v output valid from clock low ? ? 100 160 ns ns 2.5v ?? vcc ? 3.6v 1.8v ?? vcc ? 2.5v 14 t ho output hold time 0 ? ns ( note 1 ) 15 t dis output disable time ? ? 80 160 ns ns 2.5v ?? vcc ? 3.6v ( note 1 ) 1.8v ?? vcc ? 2.5v ( note 1 ) 16 t wc internal write cycle time ? 5 ms ( note 3 ) 17 ? endurance 1,000,000 ? e/w cycles ( note 2 ) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchip?s web site: www.microchip.com . 3: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete.
? 2012 microchip technology inc. preliminary ds22300a-page 5 mcp7952x/mcp7951x figure 1-1: serial input timing figure 1-2: serial output timing cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 4 2 10 9 cs sck so 10 9 13 msb out lsb out 3 15 don?t care si 14
mcp7952x/mcp7951x ds22300a-page 6 preliminary ? 2012 microchip technology inc. 2.0 pin description the descriptions of the pins are listed in tab l e 2 - 1 . figure 2-1: device pinouts 2.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initi- ated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go in standby mode as soon as the programming cycle is complete. when the device is deselected, so goes into the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 2.2 serial output (so) the so pin is used to transfer data out of the mcp795xx. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock. 2.4 serial clock (sck) the sck is used to synchronize the communication between a master and the mcp795xx. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 2.5 multifunction pin (mfp) the mfp pin is shared with the clock divider and the alarms. this pin requires an external pull-up to v cc or v bat . the pin remains low until such time that the inter- rupt flag in the register is cleared by software. this pin has a maximum sink current of 10ma. 2.6 x1, x2 the x1 and x2 pins connect to the on-board oscillator block. x1 is the input to the module and x2 is the out- put of the module. the device can be run from an external cmos signal by feeding into the x1 pin. if driving x1 the x2 pin should be a no connect. 2.7 v bat the v bat pin is a secondary supply input to maintain the clock and sram contents when v cc is removed. table 2-1: pin descriptions x1 x2 v bat vcc mfp 1 2 3 4 mcp795xx msop/tdfn cs v ss sck so si 5 6 7 10 9 8 pin name pin function v ss ground x1 xtal input, external oscillator input x2 xtal output v bat battery backup input (3v typ) v cc +1.8v to +3.6v power supply si serial input sck serial clock cs chip select mfp multifunction pin so serial output
? 2012 microchip technology inc. preliminary ds22300a-page 7 mcp7952x/mcp7951x 2.8 rtcc memory map the rtcc registers are contained in addresses 0x00h- 0x1fh. 64 bytes of user-accessable sram are located in the address range 0x20-0x5f. the sram memory is a separate block from the rtcc control and configura- tion registers. all sram locations are battery-backed- up during a v cc power fail. unused locations are not accessible. ? addresses 0x00h-0x07h are the rtcc time and date registers. these are read/write registers. care must be taken when writing to these regis- ters with the oscillator running. ? incorrect data can appear in the time and date registers if a write is attempted during the time frame where these internal registers are being incremented. the user can minimize the likelihood of data corruption by ensuring that any writes to the time and date registers occur before the contents of the second register reach a value of 0x59h. ? addresses 0x08h-0x0bh are the device configu- ration and calibration registers. ? addresses 0x0ch-0x11h are the alarm 0 registers. these are used to set up the alarm 0, the inter- rupt pin and the alarm 0 compare. ? addresses 0x12h-0x17h are the alarm 1 regis- ters. these are used to set up the alarm 1, the interrupt pin and the alarm 1 compare, alarm 1 offers a enhanced resolution of tenth and hundredths of seconds. ? addresses 0x18h-0x1fh are used for the power- down and power-up time-stamp feature. the detailed memory map is shown in table 4-1 . no error checking is provided when loading time and date registers. figure 2-2: memory map 0x00 0x07 time and date configuration and calibration alarm 0 alarm 1 time-stamp sram (64 bytes) 0x09 0x0b 0x0c 0x11 0x12 0x17 0x18 0x1f 0x20 0x5f 0x00 eeprom memory 0x00 0x07 0x08 0x0f rtcc register/sram eeprom unique id location 2 unique id location 1 eui-48/64 unique id 0xff note: 1k eeprom max address is 0x7f.
mcp7952x/mcp7951x ds22300a-page 8 preliminary ? 2012 microchip technology inc. 3.0 spi bus operation the mcp795xx is designed to interface directly with the serial peripheral interface (spi) port of many of today?s popular microcontroller families, including microchip?s pic ? microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly in soft- ware to match the spi protocol. the mcp795xx contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low for the entire operation. table 3-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data (si) is sampled on the first rising edge of sck after cs goes low. table 3-1: instruction set summary 3.1 read sequence the device is selected by pulling cs low. the various 8-bit read instructions are transmitted to the mcp795xx followed by an 8-bit address. see figure 3-1 for more details. after the correct instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. data stored in the memory at the next address can be read sequentially by continu- ing to provide clock pulses to the slave. the internal address pointer automatically increments to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to the first valid address allowing the read cycle to be continued indefinitely. the read oper- ation is terminated by raising the cs pin ( figure 1-1 ). figure 3-1: eeread sequence 3.2 nonvolatile memory write sequence prior to any attempt to write data to the nonvolatile memory (eeprom, unique id and status register) in the mcp795xx, the write enable latch must be set instruction name instruction format description eeread 0000 0011 read data from ee memory array beginning at selected address eewrite 0000 0010 write data to ee memory array beginning at selected address eewrdi 0000 0100 reset the write enable latch (disable write operations) eewren 0000 0110 set the write enable latch (enable write operations) srread 0000 0101 read status register srwrite 0000 0001 write status register read 0001 0011 read rtcc/sram array beginning at selected address write 0001 0010 write rtcc/sram data to memory array beginning at selected address unlock 0001 0100 unlock id locations idwrite 0011 0010 write to the id locations idread 0011 0011 read the id locations clrram 0101 0100 clear ram location to ? 0 ? so si sck cs 0 234567891011 1 01 0 0 0 0 01 a 7 a 6 a 5 a 4 a 1 a 0 76543210 data out high-impedance a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction
? 2012 microchip technology inc. preliminary ds22300a-page 9 mcp7952x/mcp7951x by issuing the eewren instruction ( figure 3-4 ). this is done by setting cs low and then clocking out the proper instruction into the mcp795xx. after all eight bits of the instruction are transmitted, cs must be driven high to set the write enable latch. if the write operation is initiated immediately after the eewren instruction without cs driven high, data will not be writ- ten to the array since the write enable latch was not properly set. after setting the write enable latch, the user may pro- ceed by driving cs low, issuing either an eewrite , idwrite or a swrite instruction, followed by the remainder of the address, and then the data to be writ- ten. up to 8 bytes of data can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. addi- tionally, a page address begins with xxxx 0000 and ends with xxxx x111 . if the internal address counter reaches xxxx x111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and overwrite any data that previously existed in those locations. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the nth data byte has been clocked in. if cs is driven high at any other time, the write operation will not be completed. refer to figure 3-2 and figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. while the non- volatile memory write is in progress, the status reg- ister may be read to check the status of the wip, wel, bp1 and bp0 bits. attempting to read a memory array location will not be possible during a write cycle. polling the wip bit in the status register is recommended in order to determine if a write cycle is in progress. when the nonvolatile memory write cycle is completed, the write enable latch is reset. figure 3-2: byte eewrite sequence figure 3-3: page eewrite sequence so si cs 0 234567891011 1 00 0 0 0 0 01 a 6 a 5 a 4 a 1 a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction data byte a 0 6 7 5 43 2 1 0 high-impedance twc sck a 7 si cs 91011 00 0 0 0 0 01 76543210 data byte 1 sck 0 234567 1 8 si cs 33 34 35 38 39 76543210 data byte n (8 max) sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23
mcp7952x/mcp7951x ds22300a-page 10 preliminary ? 2012 microchip technology inc. 3.3 write enable (eewren) and write disable (eewrdi) the mcp795xx contains a write enable latch. this latch must be set before any eewrite, srwrite and idwrite operation will be completed internally. the eewren instruction will set the latch, and the eewrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: ? power-up ? eewrdi instruction successfully executed ? srwrite instruction successfully executed ? eewrite instruction successfully executed ? idwrite instruction successfully executed figure 3-4: write enable sequence ( eewren ) figure 3-5: write disable sequence ( eewrdi ) sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 0
? 2012 microchip technology inc. preliminary ds22300a-page 11 mcp7952x/mcp7951x 4.0 rtcc functionality 4.0.1 rtcc register map the rtcc register space runs from 0x00 through to 0x1f. any read or write that is started within the rtcc register address space will wrap to the beginning of the rtcc registers. all of the rtcc registers are backed up from the v bat supply when v cc is not available, provided that the vbaten bit is set. any unused bits or non imple- mented addresses read back as ? 0 ?. no error checking is provided for any of the rtcc, the user may load any value. the rtcc register map is shown in ta b l e 4 - 1 . table 4-1: rtcc register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range time and configuration registers 00h tenth seconds hundredths of seconds hundredths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 10 minutes minutes minutes 00-59 03h calsgn 12/24 10 hour am/pm 10 hour hour hours 1-12 + am/pm 00 - 23 04h oscon vbat vbaten day day 1-7 05h 10 date date date 01-31 06h lp 10 month month month 01-12 07h 10 year year year 00-99 08h out sqwe alm1 alm0 extosc rs2 rs1 rs0 control reg. 09h calibration calibration 0ah reserved for future use 0bh reserved for future use alarm 0 registers 0ch 10 seconds seconds seconds 00-59 0dh 10 minutes minutes minutes 00-59 0eh 12/24 10 hour am/pm 10 hours hour hours 1-12 + am/pm 00-23 0fh alm0c2 alm0c1 alm0c0 alm0if day day 1-7 10h 10 date date date 01-31 11h 10 month month month 01-12 alarm 1 registers 12h tenth seconds hundredths of seconds hundredths of seconds 00-99 13h 10 seconds seconds seconds 00-59 14h 10 minutes minutes minutes 00-59 15h 12/24 10 hour am/pm 10 hours hour hours 1-12 + am/pm 00-23 16h alm1c2 alm1c1 alm1c0 alm1if day day 1-7 17h 10 date date date 01-31 power-down time-stamp registers 18h 10 minutes minutes 19h 12/24 10 hour am/pm 10 hours hour 1ah 10 date date 1bh day 10 month month power-up time-stamp registers 1ch 10 minutes minutes 1dh 12/24 10 hour am/pm 10 hours hour 1eh 10 date date 1fh day 10 month month
mcp7952x/mcp7951x ds22300a-page 12 preliminary ? 2012 microchip technology inc. 5.0 time and configuration registers register 5-1: hundredths of seconds 0 x 00 r/w r/w tenth seconds hundredths of seconds bit 7 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-4 tenth seconds<3:0>: tenth seconds bit 3-0 hundredths of seconds<3:0>: hundredths of seconds note 1: contains the bcd tens and hundredths of seconds. register 5-2: seconds 0 x 01 r/w r/w r/w st 10 seconds seconds bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 st: start oscillator bit st is the oscillator start bit in the mcp795xx devices. setting this bit to ? 1 ? starts the oscillator and clearing this bit to ? 0 ? stops the on-board oscillator. bit 6-4 10 seconds<2:0>: 10 seconds bit 3-0 seconds<3:0>: seconds note 1: contains the bcd seconds and 10 seconds. the range is 00 to 59. register 5-3: minutes 0 x 02 u-0 r/w r/w ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: 10 minutes bit 3-0 minutes<3:0>: minutes note 1: contains the bcd minutes and 10 minutes. the range is 00 to 59.
? 2012 microchip technology inc. preliminary ds22300a-page 13 mcp7952x/mcp7951x register 5-4: hour 0 x 03 r/w r/w r/w r/w r/w calsgn 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 calsgn: calibration sign bit bit 7 is the sign bit (calsgn) for the calibration. clearing this bit produces a positive calibration, setting this bit produces a negative calibration. bit 6 12/24 : clearing this bit to ? 0 ? enables 24-hour format, setting this bit to ? 1 ? enables 12-hour format. bit 5 10 hour: am/pm bit for 12-hour time bit 4 10 hour bit 3-0 hour<3:0> note 1: contains the bcd hour in bits <3:0>. bits <5:4> contain either the 10-hour in bcd for 24-hour format or the am/pm indicator and the 10-hour bit for 12-hour format. bit 5 determines the hour format. register 5-5: day 0 x 04 u-0 u-0 r r/w r/w r/w ? ? oscon vbat vbaten day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5 oscon: oscillator on bit this bit is set and cleared by hardware. if this bit is set, the oscillator is running; if clear, the oscillator is not running. this bit does not indicate that the oscillator is running at the correct frequency. the bit will wait 32 oscillator cycles before the bit is set. bit 4 vbat: external battery switched flag bit this bit is set by hardware when the v cc fails and the v bat is used to power the oscillator and the rtcc registers. this bit is cleared by software. bit 3 vbaten: external battery enable bit if this bit is set the internal circuitry is connected to the v bat pin. if this bit is ? 0 ? then the v bat pin is disconnected and the only current drain on the external battery is the v bat pin leakage. bit 2-0 day<2:0> note 1: contains the bcd day. the range is 1-7. also, additional bits are used for configuration and status.
mcp7952x/mcp7951x ds22300a-page 14 preliminary ? 2012 microchip technology inc. register 5-6: date 0 x 05 u-0 u-0 r/w r/w ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0> bit 3-0 date<3:0> note 1: contains the bcd date and 10 date. the range is 01-31. register 5-7: month 0 x 06 u-0 u-0 r r/w r/w ? ? lp 10 month month bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5 lp: leap year, set during a leap year and is read-only bit 4 10 month bit 3-0 month<3:0> note 1: contains the bcd month. bit 4 contains the 10 month. register 5-8: year 0 x 07 r/w r/w 10 year year bit 7 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-4 10 year<3:0> bit 3-0 year<3:0> note 1: contains the bcd year and 10 year. the range is 00-99.
? 2012 microchip technology inc. preliminary ds22300a-page 15 mcp7952x/mcp7951x register 5-9: control reg 0 x 08 r/w r/w r/w r/w r/w r/w r/w r/w out sqwe alm1 alm0 extosc rs2 rs1 rs0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 out: output polarity of mfp bit this bit sets the logic level on the mfp pin when not using this as a square wave output. bit 6 sqwe: squarewave enable bit setting this bit enables the divided output from the crystal oscillator. bit 5-4 alm<1:0>: alarm configuration bits these bits determine which alarms are active - 00 ? no alarms are active - 01 ? alarm 0 is active - 10 ? alarm 1 is active - 11 ? both alarms are active bit 3 extosc: external oscillator input bit enable bit. setting this bit will allow an external 32.768 khz signal to drive the rtcc registers, eliminating the need for an external crystal. bit 2-0 rs<2:0>: calibration mode bits sets the internal divider for the 32.768 khz oscillator to be driven to the mfp pin. the following frequencies are available. the output is responsive to the calibration register. - 000 ? 1 hz - 001 ? 4.096 khz - 010 ? 8.192 khz - 011 ? 32.768 khz - 1xx ? enables the cal output function. cal output appears on mfp if sqwe is set (1 hz nominal). note 1: when rs2 is set to enable the cal output function, the rtcc counters will continue to increment. register 5-10: calibration 0 x 09 r/w calibration bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-0 calibration value<7:0>: calibration value bits note 1: this is an 8-bit register that is used to add or subtract clocks from the rtcc counter every minute. the calsgn (0x03:7) is the sign bit and indicates if the count should be added or subtracted. the 8 bits in the calibration register, with each bit adding or subtracting two clocks, gives the user the ability to add or sub- tract up to 510 clocks per minute.
mcp7952x/mcp7951x ds22300a-page 16 preliminary ? 2012 microchip technology inc. 6.0 alarm 0 registers register 6-1: seconds 0 x 0c u-0 r/w r/w ? 10 seconds seconds bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10 seconds<2:0>: 10 seconds bit 3-0 seconds<3:0>: seconds note: this contains the seconds match for the alarm 0. register 6-2: minutes 0 x 0d u-0 r/w r/w ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: 10 seconds bit 3-0 minutes<3:0>: seconds note: this contains the minutes match for the alarm 0. register 6-3: hours 0 x 0e u-0 r/w r/w ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6 12/24: this is a copy of bit 6 in the hours register (0x03) bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0> note: this contains the minutes match for the alarm 0.
? 2012 microchip technology inc. preliminary ds22300a-page 17 mcp7952x/mcp7951x register 6-4: day 0 x 0f r/w r/w r/w r/w ? alm0c2 alm0c1 alm0c0 alm0if day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 alm0c<2:0>: alarm 0 configuration bits sets the condition on what the alarm will trigger. the following options are available: - 000 ? seconds match - 001 ? minutes match - 010 ? hours match (logic takes into account 12/24 operation) - 011 ? day match. generates interrupt at 12:00:00 am - 100 ? date match - 101 ? unimplemented, do not use - 110 ? unimplemented, do not use - 111 ? seconds, minutes, hour, day, date and month bit 3 alm0if: alarm 0 interrupt flag bit this bit is set by hardware when an alarm condition has been generated. the bit must be cleared in software. bit 2-0 day<2:0> note 1: contains the bcd day. the range is 1-7. also, additional bits are used for configuration and status. register 6-5: date 0 x 10 u-0 u-0 r/w r/w ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0> bit 3-0 date<3:0>
mcp7952x/mcp7951x ds22300a-page 18 preliminary ? 2012 microchip technology inc. register 6-6: month 0 x 11 u-0 u-0 u-0 r/w r/w ? ? ? 10 month month bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-5 unimplemented: read as ? 0 ? bit 4 10 month bit 3-0 month<3:0> note 1: month match is only available on alarm 0.
? 2012 microchip technology inc. preliminary ds22300a-page 19 mcp7952x/mcp7951x 7.0 alarm 1 registers register 7-1: hundredths of seconds 0 x 12 r/w r/w tenth seconds hundredths of seconds bit 7 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-4 tenth seconds<3:0>: tenth seconds bit 3-0 hundredths of seconds<3:0>: hundredths of seconds note 1: hundredths and tenth seconds only available on alarm 1. register 7-2: seconds 0 x 13 u-0 r/w r/w ? 10 seconds seconds bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10 seconds<2:0>: 10 seconds bit 3-0 seconds<3:0>: seconds register 7-3: minutes 0 x 14 u-0 r/w r/w ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: 10 minutes bit 3-0 minutes<3:0>: minutes
mcp7952x/mcp7951x ds22300a-page 20 preliminary ? 2012 microchip technology inc. register 7-4: hours 0 x 15 u-0 r/w r/w ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6 12/24 bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0> register 7-5: day 0 x 16 r/w r/w r/w r/w ? alm1c2 alm1c1 alm1c0 alm1if day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 alm1c<2:0>: alarm 1 configuration bits sets the condition on what the alarm will trigger. the following options are available: - 000 ? seconds match - 001 ? minutes match - 010 ? hours match (logic takes into account 12/24 operation) - 011 ? day match. generates interrupt at 12:00:00 am - 100 ? date match - 101 ? unimplemented, do not use - 110 ? unimplemented, do not use - 111 ? seconds, minutes, hour, day, date and month bit 3 alm1if: alarm 1 interrupt flag bit this bit is set by hardware when an alarm condition has been generated. the bit must be cleared in software. bit 2-0 day<2:0>
? 2012 microchip technology inc. preliminary ds22300a-page 21 mcp7952x/mcp7951x register 7-6: date 0 x 17 u-0 u-0 r/w r/w ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0> bit 3-0 date<3:0>
mcp7952x/mcp7951x ds22300a-page 22 preliminary ? 2012 microchip technology inc. 8.0 power-down time-stamp registers note: it is strongly recommended that the timesaver function only be used when the oscillator is running. this will ensure accurate functionality. register 8-1: minutes 0 x 18 u-0 r/w r/w ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10minutes<2:0>: 10 minutes bit 3-0 minutes<3:0>: minutes register 8-2: hours 0 x 19 u-0 r/w r/w ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6 12/24 : this is a copy of the status of the bit in register 0x03:6 at the time of the event bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0> register 8-3: date 0 x 1a u-0 u-0 r/w r/w ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0> bit 3-0 date<3:0>
? 2012 microchip technology inc. preliminary ds22300a-page 23 mcp7952x/mcp7951x register 8-4: month 0 x 1b r/w r/w r/w day 10 month month bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-5 day<2:0> bit 4 10 month bit 3-0 month<3:0> note 1: month match is only available on alarm 0.
mcp7952x/mcp7951x ds22300a-page 24 preliminary ? 2012 microchip technology inc. 9.0 power-up time registers note: it is strongly recommended that the timesaver function only be used when the oscillator is running. this will ensure accurate functionality. register 9-1: minutes 0 x 1c u-0 r/w r/w ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: 10 minutes bit 3-0 minutes<3:0>: minutes register 9-2: hours 0 x 1d u-0 r/w r/w ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7 unimplemented: read as ? 0 ? bit 6 12/24 : this is a copy of the status of the bit in register 0x03:6 at the time of the event bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0> register 9-3: date 0 x 1e u-0 u-0 r/w r/w ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0> bit 3-0 date<3:0>
? 2012 microchip technology inc. preliminary ds22300a-page 25 mcp7952x/mcp7951x register 9-4: month 0 x 1f r/w r/w r/w day 10 month month bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? bit 7-5 day<2:0> bit 4 10 month bit 3-0 month<3:0>
mcp7952x/mcp7951x ds22300a-page 26 preliminary ? 2012 microchip technology inc. 9.1 features 9.1.1 calibration the calibration register (0x09h) allows a number of rtcc counts to be added or subtracted (calsgn bit located at 0x03:7) each minute. this allows for calibration to reduce the ppm error due to oscillator shift. this register is volatile. the calsgn bit determines if calibration is positive or negative. a value of 0x00 in the calibration register will result in no calibration. the calibration is linear, with one bit representing two rtc clocks. the mcp795xx utilizes digital calibration to correct for the inaccuracies of the input clock source (either external or crystal). calibration is enabled by setting the value of the calibration register at address 08h. calibration is achieved by adding or subtracting a number of input clock cycles per minute in order to achieve ppm level adjustments in the internal timing function of the mcp795xx. the calsgn bit is the calibration sign bit, with a ? 1 ? indicating subtraction and a ? 0 ? indicating addition. the eight bits in the calibration register indicate the number of input clock cycles (multiplied by two) that are subtracted or added per minute to the internal timing function. the internal timing function can be monitored using the mfp output pin by setting bit 6 (sqwe) and bits <2:0> (rs2, rs1, rs0) of the control register at address 07h. note that the mfp output waveform is disabled when the mcp795xx is running in v bat mode. with the sqwe bit set to ? 1 ?, there are two methods that can be used to observe the internal timing function of the mcp795xx: method 1. rs2 bit set to ? 0 ? with the rs2 bit set to ? 0 ?, the rs1 and rs0 bits enable the following internal timing signals to be output on the mfp pin: the frequencies listed in the table presume an input clock source of exactly 32.768 khz. in terms of the equivalent number of input clock cycles, the table becomes: with regards to the calibration function, the calibration register setting has no impact upon the mfp output clock signal when bits rs1 and rs0 are set to ? 11 ?. the setting of the calibration register to a non-zero value enables the calibration function which can be observed on the mfp output pin. the calibration function can be expressed in terms of the number of input clock cycles added/subtracted from the internal timing function. with bits rs1 and rs0 set to ? 00 ?, the calibration function can be expressed as: since the calibration is done once per minute (i.e., when the internal minute counter is incremented), only one cycle in sixty of the mfp output waveform is affected by the calibration setting. also note that the duty cycle of the mfp output waveform will not necessarily be at 50% when the calibration setting is applied. with bits rs1 and rs0 set to ? 01 ? or ? 10 ?, the calibration function can not be expressed in terms of the input clock period. in the case where the msb of the calibration register is set to ? 0 ?, the waveform appearing at the mfp output pin will be ?delayed?, once per minute, by twice the number of input clock cycles defined in the calibration register. the mfp waveform will appear as shown in figure 9-1 . rs2 rs1 rs0 output signal 000 1 hz 001 4.096 khz 010 8.192 khz 011 32.768 khz rs2 rs1 rs0 output signal 000 32768 001 8 010 4 011 1 t output = (32768 +/- (2 * calreg)) t input where: t output = clock period of mfp output signal t input = clock period of input signal calreg = decimal value of calibration register setting and the sign is determined by the calsgn bit.
? 2012 microchip technology inc. preliminary ds22300a-page 27 mcp7952x/mcp7951x in the case where the msb of the calibration register is set to ? 1 ?, the mfp output waveforms that appear when bits rs1 and rs0 are set to ? 01 ? or ? 10 ? are not as responsive to the setting of the calibration register. for example, when outputting the 4.096 khz waveform (rs1, rs0 set to ? 01 ?), the output waveform is generated using only eight input clock cycles. consequently, attempting to subtract more than eight input clock cycles from this output does not have a meaningful affect on the resulting waveform. any affect on the output will appear as a modification in both the frequency and duty cycle of the waveform appearing on the mfp output pin. method 2. rs2 bit set to ? 1 ? with the rs2 bit set to ? 1 ?, the following internal timing signal is output on the mfp pin: the frequency listed in the table presumes an input clock source of exactly 32.768 khz. in terms of the equivalent number of input clock cycles, the table becomes: unlike the method previously described, the calibration setting is continuously applied and affects every cycle of the output waveform. this results in the modulation of the frequency of the output waveform based upon the setting of the calibration register. using this setting, the calibration function can be expressed as: since the calibration is done every cycle, the frequency of the output mfp waveform is constant. figure 9-1: mfp waveform rs2 rs1 rs0 output signal 1xx 1.0 hz rs2 rs1 rs0 output signal 1xx 32768 t output = (32768 +/- (2 * calreg)) t input where: t output = clock period of mfp output signal t input = clock period of input signal calreg = decimal value of calibration register setting and the sign is determined by the calsgn bit. delay
mcp7952x/mcp7951x ds22300a-page 28 preliminary ? 2012 microchip technology inc. 9.1.2 multifunction pin (mfp) pin 9 is a multifunction pin and supports the following functions: ? the value of the out bit determines the logic. ? level of the i/o. this is only available when operating from v cc . ? alarm outputs ? available in v bat mode ?f out mode ? driven from a fosc divider ? not available in v bat mode. the internal control logic for the mfp is connected to the switched internal supply bus. this allows operation in v bat mode. the alarm output is the only mode that operates in v bat mode, other modes are suspended. 9.1.3 v bat switchover if the v bat feature is not used, the v bat pin should be connected to gnd. a low value series resistor and schottky diode are recommended between the external battery and the v bat pin to reduce inrush current and also to prevent any leakage current reaching the external v bat source. the v trip point is defined as 1.5v typical. when v dd falls below 1.5v the system will continue to operate the rtcc and sram using the v bat supply. there is ~50mv hyst in the trip point changeover. the following conditions apply: for more information on v bat conditions see the rtcc best practices application note, an1365 (ds01365). 9.1.4 unique id locations when the unique id locations are preprogrammed from the factory with either an eui-48 or eui-64, the eui code is programmed into location 0x00-0x07. loca- tions 0x08-0x0f are blank (0x0f). to read the unique id location the idread command is given with the starting address. valid addresses are 0x00 through 0x0f. all 16 bytes can be read out in a single command by clocking the device. trying to access locations past 0x0f will result in the address wrapping within these 16 bytes. figure 9-2: idread command sequence to write to the unique id locations, the idwrite com- mand is used. the device must be write enabled and the correct unlock sequence must have been per- formed. see section 10.1.4, write to the unlock register for more details. the id locations can be written to using the idwrite command. the valid address is between 0x00 and 0x0f. the entire 16 bytes must be written in two groups of 8 bytes. a maximum of 8 bytes can be written at once. table 9-1: v bat changover conditions supply condition read/write access powered by v cc < v trip , v cc < v bat no v bat v cc > v trip , v cc < v bat yes v cc v cc > v trip , v cc > v bat yes v cc note: for eui-64, the data is located in address 0x00-0x07. for eui-48 locations, 0x02- 0x07 contain the data. 0x00/01 contain 0xff. so si sck cs 0 23456789101112131415161718192021 22 1 01 0 1 1 0 010000 10 76543210 instruction address byte data out high-impedance 23 32 don?t care address range is 0x00-0x0f, address counter will wrap within this range.
? 2012 microchip technology inc. preliminary ds22300a-page 29 mcp7952x/mcp7951x figure 9-3: idwrite command sequence si cs 91011 14151617181920212223 24 00 0 1 1 0 0 1 000 0 210 76543210 instruction address byte data byte 1 sck 0 234567 18 si cs 34 35 36 39 40 76543210 data byte n (8 max) sck 25 27 28 29 30 31 32 26 33 76543210 data byte 3 76543210 data byte 2 37 38 3 13
mcp7952x/mcp7951x ds22300a-page 30 preliminary ? 2012 microchip technology inc. 9.1.5 power-fail time-stamp the mcp795xx family of rtcc devices feature a power-fail time-stamp feature. this feature will save the time at which v cc crosses the v trip voltage and is shown in figure 9-4 . to use this feature, a v bat supply must be present and the oscillator must also be run- ning. there are two separate sets of registers that are used to record this information: ? the first set located at 0x18h through 0x1bh are loaded at the time when v cc falls below v trip and the rtcc operates on the v bat . the vbat (register 0x03h bit 4) bit is also set at this time. ? the second set of registers, located at 0x1ch through 0x1fh, are loaded at the time when v cc is restored and the rtcc switches to v cc . the power-fail time-stamp registers are cleared when the vbat bit is cleared in software. figure 9-4: power-fail graph 9.1.6 read status register (srread) the read status register ( srread ) instruction pro- vides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: * the write-in-process (wip) bit indicates whether the mcp795xx is busy with a nonvolatile memory write operation. when set to a ? 1 ?, a write is in progress, when set to a ? 0 ?, no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the sta- tus of the write enable latch. when set to a ? 1 ?, the latch allows writes to the nonvolatile memory, when set to a ? 0 ?, the latch prohibits writes to the nonvolatile memory. the state of this bit can always be updated via the wren or wrdi commands, regardless of the state of write protection on the status register. this bit is read-only. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction. these bits are nonvolatile. see figure 9-5 for the rdsr timing sequence. note: it is strongly recommended that the time- saver function only be used when the oscillator is running. this will ensure accu- rate functionality. v cc v trip(max) v trip(min) v ccft v ccrt power-down time-stamp power-up time-stamp 7 654 3 2 1 0 ? ???r/w r/w r r x xxx bp1 bp0welwip note: once a write status register is initiated and a read status register is attempted the new values for the nonvolatile bits will be read regardless of whether the values have been actually programmed into the device. (i.e., the values are moved to the latches prior to the write operation).
? 2012 microchip technology inc. preliminary ds22300a-page 31 mcp7952x/mcp7951x figure 9-5: read status register timing sequence so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 18 3 * data should be able to continuously be read from the status register without toggling cs , for updating of the wip and wel bits.
mcp7952x/mcp7951x ds22300a-page 32 preliminary ? 2012 microchip technology inc. 9.1.7 write status register (srwrite) the write status register ( srwrite ) instruction allows the user to select one of four levels of protec- tion for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two, or all four of the segments of the array. the partitioning is controlled as shown in ta bl e 9 - 2 . see figure 9-6 for the srwrite timing sequence. table 9-2: array protection figure 9-6: write status register timing sequence bp1 bp0 array addresses write-protected (2 kbit shown) 00 none 01 upper 1/4 (c0h-ffh) 10 upper 1/2 (80h-ffh) 11 all (00h-ffh) so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3 t wc
? 2012 microchip technology inc. preliminary ds22300a-page 33 mcp7952x/mcp7951x 9.1.8 data protection the following protection has been implemented to pre- vent inadvertent writes to the array: ? the write enable latch is reset on power-up ? a write enable instruction must be issued to set the write enable latch ? after a byte write, page write, unique id write, or status register write, the write enable latch is reset ?cs must be set high after the proper number of clock cycles to start an internal write cycle ? access to the array during an internal eeprom write cycle is ignored and programming is contin- ued ? block protect bits are ignored for uid writes 9.1.9 clear ram instruction the clear ram instruction is a 2-byte command that will reset the internal sram to the known value. using this command, all locations in the sram are set to 00h and the data value contained in the second byte of the command is ignored. figure 9-7: clrram 9.2 crystal specification and selection the mcp795xx has been designed to operate with a standard 32.768 khz tuning fork crystal. the on-board oscillator has been characterized to operate with a crystal of maximum esr of 70k ohms. crystals with a comparable specification are also suit- able for use with the mcp795xx. the table below is given as design guidance and a starting point for crystal and capacitor selection. equation 9-1: the following must also be taken into consideration: ? pin capacitance (to be included in cx2 and cx1) ? stray board capacitance the recommended board layout for the oscillator area is shown in figure 9-8 . this actual board shows the crystal and the load capacitors. in this example, c2 is cx1, c1 is cx2 and the crystal is designated as y1. when calculating the effective load capacitance, equation 9-1 can be used. so si sck cs 0 23456789101112131415 1 10 0 1 0 1 0 a7 6 5 4 1a0 instruction data high-impedance 32 0 manufacturer part number crystal capacitance cx1 value cx2 value micro crystal cm7v-t1a 7pf 10pf 12pf citizen cm200s-32.768kdzb-ut 6pf 10pf 8 pf please work with your crystal vendor. c load cx2 cx1 ? cx2 cx1 + ----------------------------- c stray + =
mcp7952x/mcp7951x ds22300a-page 34 preliminary ? 2012 microchip technology inc. figure 9-8: board layout gerber files are available on request. please contact your microchip sales representative. it is required that the final application should be tested with the chosen crystal and capacitor combinations across all operating and environmental conditions. please also consult with the crystal specification to observe correct handling and reflow conditions and for information on ideal capacitor values. for more information please see the rtcc best practices an1365 (ds01365).
? 2012 microchip technology inc. preliminary ds22300a-page 35 mcp7952x/mcp7951x 10.0 on-board memory the mcp795xx has both on-board eeprom memory and battery-backed sram. the sram is arranged as 64 bytes and is retained when v cc supply is removed. the eeprom is organized as 256 or 128 bytes. the eeprom is nonvolatile and does not require v bat sup- ply for retention. 10.1 sram the sram array is a battery-backed-up array of 64 bytes. the sram is accessed using the read and write commands, starting at address 0x20h. upon power-up the sram locations are in an unde- fined state but can be set to a known value using the clrram instruction ( figure 9-7 ). 10.1.1 sram/rtcc operation the mcp795xx contains a real-time clock and cal- endar. the rtcc registers and sram array are accessed using the same commands. the rtcc reg- isters and sram array are powered internally from the switched supply that is either connected to v cc or v bat supply. no external read/write operations are permitted when the device is running from the v bat supply. table 3-1 contains a list of the possible instruction bytes and format for device operation. 10.1.2 read sequence the part is selected by pulling cs low. the 8-bit read instruction is transmitted to the mcp79520 followed by the 8-bit address (a7 through a0). after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to pro- vide clock pulses. the internal address pointer is auto- matically incremented to the next higher address after each byte of data is shifted out. as the rtcc registers are separate from the sram array, when reading the rtcc registers set the address will wrap back to the start of the rtcc regis- ters. also when an address within the sram array is loaded the internal address pointer will wrap back to the start of the sram array. the read instruction can be used to read the registers and array indefinitely by continuing to clock the device. the read operation is terminated by raising the cs pin ( figure 10-1 ). 10.1.3 write sequence as the rtcc registers and sram array do not require the wren sequence like the nonvolatile memory, the user may proceed by setting the cs low, issuing the write instruction, followed by the address, and then the data to be written. as no write cycle is required for the rtcc registers and sram array the entire con- tents can be written in a single command. for the last data byte to be written to the rtcc regis- ters and sram array, the cs must be brought high after the last byte has been clocked in. if cs is brought high at any other time, the last byte will not be written. refer to figure 10-2 for more detailed illustrations on the write sequence. figure 10-1: read sequence so si sck cs 0 23456789101112131415161718192021 22 1 01 0 1 0 0 01 a7 6 5 4 1a0 76543210 instruction address byte data out high-impedance 23 32 don?t care the address will rollover to the start of either the rtcc registers or sram array.
mcp7952x/mcp7951x ds22300a-page 36 preliminary ? 2012 microchip technology inc. figure 10-2: write sequence 10.1.4 write to the unlock register the mcp795xx contains a protected area of 64 bits that can be used to hold a unique id, such as a serial number or mac address code. to gain write access to these locations, a specific sequence is required. any deviation from this sequence will reset the lock on these locations. once these locations have been unlocked they have to be written to in the next com- mand by issuing the correct command. a write to a dif- ferent location will lock the id locations and clear the wel bit. the following is a list of strict conditions which have to be followed before the unique locations can be written to: ? eewren instruction successfully executed ? unlock 0x55 instruction successfully executed ? unlock 0xaa instruction successfully executed to issue each unlock instruction the unlock com- mand is sent followed by 0x55. then in a separate command the unlock command is issued followed by 0xaa. it is a requirement that each command be sepa- rate, that is cs must toggle between each command. information on how to read and write the id locations is detailed in section 9.1.4, unique id locations . figure 10-3: unlock sequence so si sck cs 0 23456789101112131415161718192021 22 1 00 0 0 0 0 0 a7 6 5 4 1a0 76543210 instruction address byte data byte high-impedance 23 32 1 so si sck cs 0 23456789101112131415 1 10 0 1 0 0 0 7654 10 instruction data high-impedance 32 0
? 2012 microchip technology inc. preliminary ds22300a-page 37 mcp7952x/mcp7951x 11.0 packaging information 11.1 package marking information part number 1st line marking codes msop tdfn mcp79520 79520i 520i mcp79510 79510i 510i MCP79521 79521i 521i mcp79511 79511i 511i mcp79522 79522i 522i mcp79512 79512i 512i note: t = temperature grade nn = alphanumeric traceability code legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 10-lead msop (3x3 mm) example 10-lead tdfn example xxxx yyww nnn pin 1 79520i 210abc xxxx yyww nnn pin 1 520i 1135 abc
mcp7952x/mcp7951x ds22300a-page 38 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds22300a-page 39 mcp7952x/mcp7951x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp7952x/mcp7951x ds22300a-page 40 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds22300a-page 41 mcp7952x/mcp7951x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp7952x/mcp7951x ds22300a-page 42 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds22300a-page 43 mcp7952x/mcp7951x appendix a: revision history revision a (04/2012) initial release.
mcp7952x/mcp7951x ds22300a-page 44 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds22300a-page 45 mcp7952xx/mcp7951xx the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration s. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
mcp7952xx/mcp7951xx ds22300a-page 46 preliminary ? 2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22300a mcp7952xx/mcp7951xx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2012 microchip technology inc. preliminary ds22300a-page 47 mcp7952xx/mcp7951xx product identification system to order or obtain information, e.g., on pric ing or delivery, refer to the factory or the listed sales office. not every possib le ordering combination is listed below . mcp795 i /xx package tem p range base part base part no.: mcp795 = spi rtcc memory: 1 = 1 kbit ee, 64 bytes sram 2 = 2 kbits ee, 64 bytes sram id/mac address: 0=blank 1 = eui-48? mac address 2 = eui-64? mac address t/r: blank = tube t = tape and reel temperature range: i=-40 ? c to +85 ? c package: ms = 10-pin msop mn = 10-pin tdfn examples: a) mcp79510-i/ms: 1k eeprom, blank id, industrial temperature, msop package b) mcp79512-i/ms: 1k eeprom, eui-64?, industrial temperature, msop package c) mcp79511t-i/mn: 1k eeprom, eui-48?, industrial temperature, tape and reel, tdfn package d) mcp79520-i/ms: 2k eeprom, blank id, industrial temperature, msop package e) mcp79522-i/ms: 2k eeprom, eui-64?, industrial temperature, msop package f) MCP79521t-i/mn: 2k eeprom, eui-48?, industrial temperature, tape and reel, tdfn package 1 memory 0 unique t t/r id ?
mcp7952xx/mcp7951xx ds22300a-page 48 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds22300a-page 49 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620761984 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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